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Memory Sync Controller III
SDA 9220-5
Preliminary Data Features Large area flicker elimination through field doubling Additional elimination of interline flicker in field mode Field switching and selection in field mode Noise and cross-color reduction Stills 9-image display, still-in-picture, picture-in-still with different frame versions q Zoom with selection of enlarged picture segment (8 x 12 positions) q Pin-programmable operation without standard conversion
q q q q q q
MOS IC
P-LCC-44-1
Type SDA 9220-5 Functional Description
Ordering Code Q67100-H5087
Package P-LCC-44-1 (SMD)
The MSC III is a component of the TV-SAM Featurebox and is responsible for driving the picture memory devices (TV-SAMs) and generating sync signals (figure 6). Together with the other devices of the Featurebox it enhances picture quality and offers a number of special operating modes. The MSC III is set via the I2C Bus, it being possible to switch the I2C Bus address by hardware so that implementation of a simple frame Featurebox is possible in conjunction with the signal MUX supplied by the MSC III. Other major output signals of the SDA 9220-5, in addition to the clocks LL3X (13.5 MHz) and LL1.5X (27 MHz), are the memory-driving signals (RA, RB, WT, RE, SCAD, SCA) and the sync signal CSY for the teletext device. The horizontal sync signals (HS2, BLN2) and the vertical sync signals (VS1, VS2) are also generated.
Semiconductor Group
117
01.94
SDA 9220-5
Circuit Description The MSC III can be divided into the following function blocks (figure 6): - - - - Sync-signal generator Memory controller Clock generator I2C Bus receiver
The sync-signal generator uses signals VS and BLN to produce the horizontal and vertical sync signals BLN2, HS2, VS1 and VS2. It supplies the composite sync signal CSY for the 100-Hz teletext, the control signal MUX for implementing a simple frame Featurebox and the frame signal FRM for inserting a colored frame in multi-picture, still-in-picture and picture-in-still modes. Signal CFH is output to prevent the bottom flutter effect in the video cassette recorder mode. In operation without standard conversion (pin-programmable) signals BLN2, VS2 and FRM are switched from double to single line/field frequency. Outputs CSY and HS2 are not required in this case. The memory controller produces the driving signals (RA, RB, WT, RE) and the addresses (SAR, SAC) for the memory devices (TV-SAMs). In addition, it produces the DREQ pulses used for requesting data from the picture processor during operation with reduced pictures. Two refresh operations are performed in the memory for each TV line. The clock generator consists essentially of a PLL which generates the internal and exported system clocks from input clock LL3 or LL1.5 and synchronizes them with the horizontal blanking signal. The MSC can be set to one of the two input frequencies via input LLSEL. For the possible use of the Featurebox as a channel scanner, the PLL incorporates a crystal-controlled reference clock to ensure an undisturbed clock supply for memory output (stills sequence) during channel-switching phases. All modes (except switching off the standard conversion) are set by appropriate programming of the I2C Bus data bytes. When the operating voltage is switched on, all bits of the associated control registers are set to 0. The address of the I2C Bus is set with signal ADR (24H or 26H).
Semiconductor Group
118
SDA 9220-5
Detailed Circuit Description Picture Formats The MSC forms part of a digital television system with line-locked scanning frequency. The nominal word rate is 13.5 MHz for luminance and 3.375 MHz for each of the U and V color components. The active region of a TV line is identified by the high time interval of BLN. It comprises 720 pixels for luminance and 180 pixels each for U and V and is stored in its entirety. In the 50-Hz standard a field consists of 287.5 lines and in the 60-Hz standard of 243.5 lines. 288 lines are stored in the 50-Hz standard (lines 23-310 of the first field, lines 336-623 of the second field) and 243 lines in the 60-Hz standard (lines 17-259 of the first field, lines 280-522 of the second field), (figure 1). In the 9-image mode a field without a frame consists of 208 pixels per line for luminance and 2 x 52 pixels per line for chrominance, with four pixels being lost for luminance and 2 x 1 for chrominance with memory or display frames. The number of lines without a frame is 84 for the 50-Hz standard and 71 for the 60-Hz standard. Two lines less are displayed with a frame (figures 2 and 3). In the picture-in-still (PIS) and still-in-picture (SIP) modes a field without a frame or having a display frame is of the same size as a 9-image window. With the memory frame, however, eight pixels are lost for luminance and 2 x 2 for chrominance (figure 4). For generating the windows in the modes 9-image display, PIS and SIP the picture data are filtered horizontally and vertically in the picture processor and reduced by a factor of three. In the zoom mode a segment of the stored picture is enlarged by a factor of two by displaying each pixel twice as long and each line twice. The position of this picture segment is selectable. Eight vertical and twelve horizontal positions can be set by the I2C Bus (figure 5). Random Interlace The phase of VS relative to HS and the active picture content is measured at the input. At the output VS2 is generated in the same phase relation to HS2 and the picture content. Despite the random interlacing this means that standard picture conversion is possible without any visible interference. Display Raster There are three ways of displaying the field sequence: one is without interlace and two are with interlace, i.e. with a 50-Hz or 60-Hz interlace frequency or a 100-Hz or 120-Hz interlace frequency respectively. In what follows these are referred to symbolically as , or . They are produced by a suitable sequence of the vertical sync pulses VS2 for the standard-converted video signal. The symbols n, n denote the vertical sync phases of the pulses (VS, VS2) referred to the horizontal blanking signals (BLN, BLN2), i.e. n when the positive vertical sync edge falls within one blanking half cycle and n when it falls within the complementary blanking half cycle. Normally the input signal will be as follows: (n-1, n-1) (n, n) (n+1, n+1) with n and n virtually constant. Figures 15, 16, 17, 18 and 19 show the sequence obtained for output signal VS2 when using one of the three operating modes.
Semiconductor Group
119
SDA 9220-5
The standard conversion (SC) function can be activated via pin NW
q The following correlation exists:
Low level at pin NW: Mode without standard conversion High level at pin NW: Mode with standard conversion If the standard conversion is switched on, there is a 100-(120-) Hz field frequency in the 50(60)-Hz standard. Field sequence with SC: A() A() B() B() 1) Field sequence without SC: A() B() The following functions can be set on the I2C Bus 2) interface:
q Still
q
q
q
q q q
A() A() A() A() or B() B() B() B() Field sequence with SC and without interlace: A() A() A() A() or B() B() B() B() Field sequence without SC and without interlace: A() A() or B() B() Teletext text mode: AVT() AVT() AVT() AVT() or: AVT() AVT() AVT() AVT() Teletext mixed mode: with SC AVT() AVT() AVT() AVT() without SC AVT() AVT() Teletext field mode: In this mode every second field is written to the field memory. The display raster is freely selectable. Although the vertical resolution of the TV picture is slightly less in this mode, the lack of background edge flicker improves the visual effect in teletext mixed mode. An improvement in the picture can also be achieved with VCR signals in the special modes. It is also possible to select a particular field; this is useful for specific requests. HS2 phase: Programmable between 0 and 32 s in increments of approx. 300 ns (for delay equalization between picture generation and deflection). Write operation delay owing to delay in the picture processor for noise reduction can be set between 0 and 14 or 16 and 30 LL3X clocks. When the color frame is used, the picture-in-picture and multi-picture modes have to be activated without the software frame because the two are not identical. The picture-in-picture and multi-picture modes cannot be switched on in the field mode; there may otherwise be no gray backing for the frame function, depending on the field. The field mode can only be activated one field after the picture-in-picture or multi-picture mode.
Field sequence with SC and interlace:
1) Field content
A()
Vertical sync phase referred to horizontal sync pulse (raster)
2) I2C Bus: Bus system patented by Philips
Semiconductor Group
120
SDA 9220-5
q When switching from free running to line-locked mode, the following maximum synchronization
times can occur for standard signals: a) Vertical synchronization at 50 (60) Hz and 100 (120) Hz: a) Horizontal synchronization at 50 (60) Hz: 100 (120) Hz: Device Interfaces
220 (183) ms 100 (83) ms 100 (75) ms
The interfaces of this device are designed to work with the CSG SDA 9257 and triple ADC SDA 9205-2, or DMSD/CGC, the TV-SAMs SDA 9251-2X and Picture Processor SDA 9290-5. The standard conversion function can be enabled and disabled on one pin. All other functions are set on an I2C Bus interface. I2C Bus Interface 1. Functional Overview The following control signals are received on the I2C Bus: - - - - - - - - - - - - - - - - - - - - Synchronization (EXSYN) Blanking (BLK) Control for frame mode (MUXI, MUXS) VS noise reduction (VNR) 50/60-Hz standard (VERT) Deflection raster (VDM 1-0) Field mode with field changeover (FLDM, FLDC, FLDF) Delay compensation for write channel (WDEL 4-0) Still (STB) Frame (FR) Write mode (WM 1-0) Picture position for 9-image, picture-in-picture (VPOS 1-0, HPOS 1-0) Zoom mode (ZM) Position of zoom detail (ZV 2-0, ZH 3-0) NTSC mode with 864 pixels per line (N864) HS2 phase relation (HP 6-0) Disabling of frame display signal (FRDIS) Delay of frame display signal (FRD 6-0) Duration of CFH signal (CFHW 3-0) Position of CFH signal (CFHP 3-0)
Semiconductor Group
121
SDA 9220-5
2. Description Slave Address: 0 0 1 0 0 1 ADR
Receiver Format: S Slave Address 0A Sub Address A Data Byte AP
S: Start condition A: Acknowledge P: Stop condition
Data Byte Formats: Function Control 1 Control 2 Control 3 HS2 phase FRM delay CFH control Subaddress D7 00 01 02 04 05 06
FLDM STB ZM N864 FRDIS
Data Byte D6
FLDC FR ZV2 HP6 FRD6
D5
MUXI FLDF WM1 ZV1 HP5 FRD5
D4
MUXS
D3
VNR
D2
VERT
D1
VDM1
D0
VDM0
EXSYN BLK
WDEL4 WDEL3 WDEL2 WDEL1 WDEL0 WM0 ZV0 HP4 FRD4 VPOS1 ZH3 HP3 FRD3 VPOS0 ZH2 HP2 FRD2 CFHP2 HPOS1 HPOS0 ZH1 HP1 FRD1 CFHP1 ZH0 HP0 FRD0 CFHP0
Zoom control 03
CFHW3 CFHW2 CFHW1 CFHW0 CFHP3
The subaddress is incremented automatically. When the operating voltage is applied (power-up reset), all registers are set to 0.
Semiconductor Group
122
SDA 9220-5
3. Detailed Tables Control 1 (subaddress 00) Synchronization External synchronization (line-locked) Internal synchronization (free-running) Blanking Picture enabled Picture blanked MUX Invert, MUX Strobe (Figure 9b shows the functional diagram of MUX) MUX = L MUX toggles with VS2 (for VS1 = H change to L) MUX = H MUX toggles with VS2 (for VS1 = H change to H) VS Noise Reduction Mode 1 (window) Mode 2 (flywheel) 50/60-Hz-Standard 50-Hz standard 60-Hz standard Deflection Raster (with standard conversion) (w/o standard conversion) (with standard conversion) (w/o standard conversion) (with standard conversion) not defined (w/o standard conversion) Not defined 0 0 1 1 Control Bit EXSYN (D7) 0 1 Control Bit BLK (D6) 0 1 Control Bit MUXI (D5) 0 0 1 1 MUXS (D4) 0 1 0 1
Control Bit VNR (D3) 0 1 Control Bit Vert (D2) 0 1 Control Bit VDM 1 (D1) VDM 0 (D0) 0 1 0 1
Semiconductor Group
123
SDA 9220-5
Control 2 (subaddress 01) Field Mode Normal mode (both fields) Field mode (only one field) Field Switching in Field Mode For FLDF = L: Change of field; (no reference to a specific field) For FLDF = H: Field 1 displayed Field 2 displayed Field Mode Feature Selection Free-running field mode without field reference Field mode with field reference Control Bit FLDM (D7) 0 1 Control Bit FLDC (D6) 01 10 0 1 Control Bit FLDF (D5) 0 1
Write Operation Delay in LL3 Periods (from rising edge of BLN) Delay 0 to Delay 14 Delay 16 to Delay 30 Not defined
Control Bit WDEL4 (D4) 0 0 1 1 x WDEL3 (D3) 0 1 0 1 1 WDEL2 (D2) 0 1 0 1 1 WDEL1 (D1) 0 1 0 1 1 WDEL0 (D0) 0 0 0 0 1
Semiconductor Group
124
SDA 9220-5
Control 3 (subaddress 02) Still Moving image Still Frame 9-image picture, picture-in-picture without frame 9-image picture, picture-in-picture with frame Write Mode Normal mode (NM) 9-image picture mode (MP) Picture-in-still (PIS) Still-in-picture (SIP) Vertical Picture Position for 9th Image Vertical position 0 Vertical position 1 (not allowed for PIS and SIP) Vertical position 2 Not defined Horizontal Picture Position for 9th Image Horizontal position 0 Horizontal position 1 (not allowed for PIS and SIP) Horizontal position 2 Not defined 0 0 1 1 0 0 1 1 Control Bit HPOS 1 (D1) HPOS 0 (D0) 0 1 0 1 0 0 1 1 Control Bit VPOS 1 (D3) VPOS 0 (D2) 0 1 0 1 Control Bit STB (D7) 0 1 Control Bit FR (D6) 0 1
Control Bit WM 1 (D5) WM 0 (D4) 0 1 0 1
Semiconductor Group
125
SDA 9220-5
Zoom Control (subaddress 03) Zoom Normal Zoom Vertical Position of Zoomed Detail ZV 2 (D6) Vertical position 0 to Vertical position 7 Horizontal Position of Zoomed Detail ZH 3 (D3) Horizontal position 0 to Horizontal position 11 Not defined
x: don't care
Control Bit ZM (D7) 0 1 Control Bit ZV 1 (D5) 0 1 Control Bit ZH 2 (D2) 0 0 1 ZH 1 (D1) 0 1 x ZH 0 (D0) 0 1 x 0 1 1 ZV 0 (D4) 0 1 0 1
HS2 Phase (subaddress 04) Switching in 60-Hz Mode (VERT = 1) 858 pixels per line 864 pixels per line HS2 Phase HP 6 (D6) 0 steps to 108 steps 0 1 HP 5 (D5) 0 1 HP 4 (D4) 0 0 Control Bit HP 3 (D3) 0 1 HP 2 (D2) 0 1 HP 1 (D1) 0 0 HP 0 (D0) 0 0 Control Bit N864 (D7) 0 1
One step corresponds to eight LL1.5 cycles (approx. 300 ns).
Semiconductor Group
126
SDA 9220-5
FRM Delay (subaddress 05) FRM Disable Frame display signal FRM enable Frame display signal FRM disable (FRM = L) Delay for Frame Display Signal 0 LL1.5 cycles to 127 LL1.5 cycles Control Bit FRD 6 (D6) 0 1 FRD 5 (D5) 0 1 FRD 4 (D4) 0 1 FRD 3 (D3) 0 1 FRD 2 (D2) 0 1 FRD 1 (D1) 0 1 FRD 0 (D0) 0 1 Control Bit FRDIS (D7) 0 1
CFH Control (subaddress 06) CFH Width (H level) CFHW3 (D7) 0 halfline to 15 halflines CFH Position Before VS CFHP3 (D3) 3 halflines to 18 halflines 0 1 0 1 Control Bit CFHW2 (D6) 0 1 CFHW1 (D5) 0 1 CFHW0 (D4) 0 1
Control Bit CFHP2 (D2) 0 1 CFHP1 (D1) 0 1 CFHP0 (D0) 0 1
Semiconductor Group
127
SDA 9220-5
Figure 1 Picture Format, Normal Mode Semiconductor Group 128
SDA 9220-5
Figure 2 Picture Formats for 9-Image Mode Semiconductor Group 129
SDA 9220-5
Figure 3 Picture Formats for 9-Image Mode, PIS and SIP with Display Frame Semiconductor Group 130
SDA 9220-5
Figure 4 Picture Formats for Picture-in-Still, Still-in-Picture Semiconductor Group 131
SDA 9220-5
Figure 5 Zoomed Picture Segments Semiconductor Group 132
SDA 9220-5
Figure 6 Block Diagram 1, Featurebox with Standard Conversion Semiconductor Group 133
SDA 9220-5
Figure 7 Block Diagram 2 Memory Sync Controller
Semiconductor Group
134
SDA 9220-5
Figure 8 Pin Configuration (top view)
Semiconductor Group
135
SDA 9220-5
Pin Definitions and Functions Pin No. Symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Function Analog ground Analog supply voltage PLL filter Test pin Test pin Test pin 27-MHz clock Select standard conversion Serial clock Serial address clock Clock Digital ground Digital supply voltage Row enable Read transfer Serial row address Read transfer Serial column address and mode Write transfer Digital ground Write inhibit Data request Write-enable input for direct disabling of write operation for field memory Data-request signal in 9-image mode for reduced picture data; at same time I2C Bus sync signal for picture processor Normally on VDD (active low) Position supply voltage (+ 5 V) for digital part Positive supply voltage Control signal for TV-SAM Via port A of TV-SAM For TV-SAM Via port B of TV-SAM For TV-SAM Via port C of TV-SAM Positive supply voltage (+ 5 V) for analog part Connecting pin for PLL filter Test pin; must be connected to VSS for normal mode Test pin; must be connected to VSS for normal mode Test pin; must be connected to VSS for normal mode 27-MHz clock for devices of Featurebox generated by PLL Standard-conversion switching; high level on this pin means that standard conversion is activated Serial clock for port A of TV-SAM Serial address clock for TV-SAM 13.5-MHz clock for the devices of the Featurebox generated by PLL Description
VSSA VDDA
RST TE2 TE1 TE0 LL1.5X NW SCA SCAD LL3X
VSS VDD
RE RA SAR RB SAC WT
VSS
WEI DREQ
23 24 25
RESQ RESI
Reset output Reset input Digital supply voltage
VDD
Semiconductor Group
136
SDA 9220-5
Pin Definitions and Functions (cont'd) Pin No. Symbol 26 27 28 29 30 31 32 33 34 35 36 37 38 ADR ZM VS VS1 MUX LLSEL CFH OSCI OSCQ SCL SDA CSY FRM Function Address select Zoom signal Vertical sync Vertical sync MUX switching Select clock input Clock frequency hold Crystal oscillator input Crystal oscillator output Serial clock I2C Bus Serial data I2C Bus Composite sync Horizontal and vertical sync pulses for Teletext device in standard-conversion mode Crystal clock as reference for recovery in tuner scanning mode Description 24H for ADR = 0 or 26H for ADR = 1 Control signal for Featurebox output interface IC: supplies high level in zoom mode Input determines vertical position of TV picture for 50-or 60-Hz field frequency Output; noise suppressed Switching signal for implementing simple frame Featurebox A 27-MHz clock selected for LLSEL = low For elimination of bottom flutter effect in VCR mode
Display frame signal Control signal output for possible insertion of colored frame in multi-picture, picture-in still and still-inpicture modes Horizontal sync display Horizontal blank display Horizontal blank Input clock Digital ground Horizontal pulse for standard-converted picture (31.25 / 31.47 kHz) Blanking signal for identifying active picture line for data readout Blanking signal input; high phase identifies active picture line 13.5 or 27 MHz
39 40 41 42 43 44
HS2 VS2 BLN2 BLN LLIN
Vertical sync display Vertical sync pulse for data readout
VSS
Semiconductor Group
137
SDA 9220-5
Absolute Maximum Ratings (all voltages are referred to VSS) Parameter Ambient temperature Storage temperature Thermal resistance Supply voltage Input voltage Total power dissipation Operating Range Supply voltage Supply current digital Supply current analog Ambient temperature Symbol min. Limit Values typ. max. 70 125 50 - 0.3 - 0.3 6 6 1.25 C C K/W V V W 0 - 55 Unit Remarks
TA Tstg Rth SA VDD VI Ptot
VDD IDDD IDDA TA
4.5
5 200 2
5.5 240 2.3 70
V mA mA C Sum pins 13, 27 Pin 2
0
Semiconductor Group
138
SDA 9220-5
Characteristics Parameter Symbol min. Limit Values typ. max. Unit Test Condition
Input Clock LLIN = 13.5 MHz/LLSEL = High or Open (refer to figure 9 c) Period H-pulse width L-pulse width H-input voltage L-input voltage TLLIN 68 25 25 2 0.8 74 80 ns ns ns V V
tWH tWL VIH VIL
Input Clock LLIN = 27 MHz/LLSEL = Low (refer to figure 9 c) Period H-pulse width L-pulse width H-input voltage L-input voltage TLLIN 34 10 10 2 0.8 37 40 ns ns ns V V
tWH tWL VIH VIL
Input Signal BLN, VS, WEI/Reference Clock: LLIN = 13.5 MHz (refer to figure 9c) Setup time Hold time H-input voltage L-input voltage H-input current L-input current
tSU tIH VIH VIH IIH IIL
14 5 2 0.8 - 80 - 100 - 500 - 500
ns ns V V A A
Input Signal BLN, VS, WEI/Reference Clock: LLIN = 27 MHz (refer to figure 9c) Setup time Hold time H-input voltage L-input voltage H-input current L-input current
tSU tIH VIH VIL IIH IIL
7 6 2 0.8 - 80 - 100 - 500 - 500
ns ns V V A A
Semiconductor Group
139
SDA 9220-5
Characteristics (cont'd) Parameter Symbol min. Limit Values typ. max. Unit Test Condition
Output Clock LL1.5X/Reference Clock: LLIN (refer to figure 9a) Period H-pulse width L-pulse width Clock skew *) Load capacitance H-output voltage L-output voltage TLL1.5X 34 12 12 0 2.4 0.4 15 50 37 40 ns ns ns ns pF V V
tWH tWL tSK CL VQH VQL
IQH = - 2.5 mA IQL = 5 mA
Output Clock LL3X/Reference Clock: LLIN (refer to figure 9a) Period H-pulse width L-pulse width Clock skew *) Load capacitance H-output voltage L-output voltage
*) With steady-state PLL.
TLL3X
68 25 25 0 2.4
74
80
ns ns ns
tWH tWL tSK CL VQH VQL
15 50 0.4
ns pF V V
IQH = - 2.5 mA IQL = 5 mA
Semiconductor Group
140
SDA 9220-5
Characteristics (cont'd) Parameter Symbol min. Limit Values typ. max. Unit Test Condition
Output Clock SCA/Reference Clock: LL1.5X (refer to figure 9a) H-pulse width L-pulse width Clock skew **) Load capacitance H-output voltage L-output voltage Period
tWH tWL tSK CL VQH VQL
TSCA1 TSCA2 ***)
10 10 0 2.4
25 15 50 0.4
ns ns ns pF V V ns ns
IQH = - 2.5 mA IQL = 5 mA
Normal mode with standard conversion Normal mode without standard conversion or zoom mode with standard conversion Zoom mode without standard conversion
34 68
37 74
40 80
TSCA3 ***)
136
148
160
ns
Output Clock SCAD/Reference Clock: LL3X (refer to figure 9a) Period H-pulse width L-pulse width Clock skew *) Load capacitance H-output voltage L-output voltage TSCAD 34 12 12 - 15 2.4 0.4 0 50 37 40 ns ns ns ns pF V V
tWH tWL tSK CL VQH VQL
IQH = - 2.5 mA IQL = 5 mA
*) With steady-state PLL and provided that the capacitive load of the reference clock is identical or more. **) With steady-state PLL and provided that the capacitive load of the reference clock is identical or less. ***) TSCA2/3 are generated from TSCA1 (by blanking the high phases).
Semiconductor Group
141
SDA 9220-5
Characteristics (cont'd) Parameter Symbol min. Limit Values typ. max. Unit Test Condition
Output Signals: BLN2, FRM, ZM, HS2, VS2/Reference Clock: LL1.5X (refer to figure 9b) Delay time (for HS2, VS2) Delay time (for BLN2, FRM, ZM) Hold time Load capacitance H-output voltage L-output voltage
tQD tQD tQH CL VQH VQL
2.4 6
20 25
ns ns ns
30 0.4
pF V V
IQH = - 2.5 mA IQL = 5 mA
Output Signals: WT, RB, CSY, VS1, MUX, DREQ, CFH/Reference Clock: LL3X (refer to figure 9b) Delay time Hold time Load capacitance for WT, RB Load capacitance for CSY, VS1, DREQ, CFH H-output voltage L-output voltage
tQD tQH CL CL VQH VQL
2.4 6
25 50 30
ns ns pF pF V
IQH = - 2.5 mA IQL = 5 mA
0.4
V
Output Signals: RA/Reference Clock: SCA (refer to figure 9b) Delay time Hold time Load capacitance H-output voltage L-output voltage
tQD tQH CL VQH VQL
2.4 0
15 50 0.4
ns ns pF V V
IQH = - 2.5 mA IQL = 5 mA
Semiconductor Group
142
SDA 9220-5
Characteristics (cont'd) Parameter Symbol min. Limit Values typ. max. Unit Test Condition
Output Signals: SAR, SAC, RE/Reference Clock: SCAD (refer to figure 9b) Delay time for SAR, SAC Delay time for RE Hold time Load capacitance H-output voltage L-output voltage PLL-Filter Currents Charge current Charge current Discharge current Discharge current
tQD tQD tQH CL VQH VQL
2.4 6
25 20 50 0.4
ns ns ns pF V V
IQH = - 2.5 mA IQL = 5 mA
ICH ICH IDCH IDCH
80 70 - 80 - 70
250 250 - 300 - 300
A A A A
VQL = 1.9 V VQL = 2.9 V VQL = 1.9 V VQL = 2.9 V
Filter Elements (see figure 10a)
CF1 1.5 nF, RF 1.8 k, CF2 100 pF
Crystal (see figure 10b) Nominal frequency Effect of temperature and accuracy of adjustment Temperature range Load capacitance Resonant impedance Equivalent parallel C Crystal load
fQ
f/fQ
6.7500
MHz
TA CL ZR CO
0 33 0.5 60
70
C pF
7 20 % pF 0.1 mW
Semiconductor Group
143
SDA 9220-5
Figure 9 Timing Diagram (for characteristics of SDA 9220-5) Semiconductor Group 144
SDA 9220-5
a) Filter Circuitry
b) Crystal Circuitry
Figure 10 Circuit Configuration for Filter and Crystal Reset Behavior of SDA 9220-5 The circuitry has sensor logic for separately detecting values below the minimum supply level on the VDDA and the two VDD pins. A reset cycle is initiated whenever such values are detected; the reset time is preset by charging and discharging the pin capacitance of the reset input pin which is not normally connected. This time can be extended by connecting RESI with an external capacitance. The RESI pin can also be connected directly with a signal; a RES low level enables reset, a RES high level terminates the reset. The internal circuit reset status is output via reset RESQ and can then be used as an active low signal (low level = reset status). During the reset phase all the output clocks generated by MSC (LL1.5X, LL3X, SCA and SCAD) are kept at low level. Upon completion of the reset the SDA 9220-5 is in its basic (line-locked) mode. If no clock is applied to LLIN at this point of time, the VCO in the PLL oscillates at its free-running frequency (5-20 MHz) and enables all the output clocks derived from it. - Typical Control Values for the Reset System Initiation level for reset on VDD Low level on RESI High level on RESI Output low level on RESQ Output high level on RESQ
VDDR VRIL VRIH VQL VQH
< 3.9 V < 1.5 V > 2.3 V 0.4 V (IQL = 5 mA) 2.4 V (IQH = - 2.5 mA)
Semiconductor Group
145
SDA 9220-5
Figure 11 Application Circuit for Eliminating Bottom Flutter Semiconductor Group 146
SDA 9220-5
Figure 12 Timing Diagrams, Horizontal Sync Signals for Standard Conversion Note: The figures indicate the number of LL3-clock periods Semiconductor Group 147
SDA 9220-5
Figure 13 Timing Diagrams, Horizontal Sync Signals without Standard Conversion Note: The figures indicate the number of LL3-clock periods Semiconductor Group 148
SDA 9220-5
Figure 14 Memory Basic Cycle for Normal Mode with Standard Conversion and 864 Pixels per Line Semiconductor Group 149
WTN: --- Write operation delay 0 or 16 LL3X clocks ----- Write operation delay 1-14 or 17-30 LL3X clocks
SDA 9220-5
Figure 15
Semiconductor Group
150
SDA 9220-5
Figure 16
Semiconductor Group
151
SDA 9220-5
Figure 17
Semiconductor Group
152
SDA 9220-5
Figure 18
Semiconductor Group
153
SDA 9220-5
Figure 19
Semiconductor Group
154
SDA 9220-5
Operation with Standard Conversion
Figure 20a VS/VS2 Phase Relation for Mode A() A() B() B() and VS Edge in First BLN-Half Cycle (VNR Bit = 1)
Semiconductor Group
155
SDA 9220-5
Figure 20b VS/VS2 Phase Relation for Mode A() A() B() B() and VS Edge in Second BLN-Half Cycle (VNR Bit = 1)
Semiconductor Group
156
SDA 9220-5
Figure 21 Timing Diagram, CSY-Pulse Sequency B) C) *) **) Start of TV line 3 (1st field) or 316/266 (2nd field) before standard conversion (50/60 Hz) Start of TV line 3 of each field after standard conversion (100/120 Hz) Alternative Rising edge of CSY comes four LL3X cycles before falling edge of BLN2
Semiconductor Group
157
SDA 9220-5
Figure 22 Timing for I2C Bus
Parameter Clock frequency Inactive time before start of new transmission Hold time for start condition (after this time first clock pulse is generated) Low clock phase High clock phase Setup time for data Rise time for SDA and SCL signals Fall time for SDA and SCL signals Setup time for SCL clock in stop condition
Symbol
Limit Values min. max. 100 0 4.7 4.0 4.7 4.0 250 1 300 4.7
Unit kHz s s s s ns s ns s
fSCL tBUF tHD; STA tLOW tHIGH tSU; DAT tTLH tTHL tSU; STO
All values are referred to specified input levels VIH and VIL.
Semiconductor Group
158

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